The present invention relates to a high voltage detector circuit, and particularly to that for discriminating whether voltage impressed to its input terminal is higher or not than power supply voltage thereof.
An LSI (Large Scale Integrated circuit) having a rewritable non-volatile memory is provided with a variable voltage supply Vpp which supplies a high voltage (about 12 to 15V) when writing or erasing the non-volatile memory and a low voltage having the same voltage level (about 3 to 5V) as an ordinary power supply Vcc when reading out the non-volatile memory. The non-volatile memory is set either in write mode or in read-out mode according the output of a high voltage detector circuit provided in the LSI for discriminating whether the variable voltage supply Vpp supplied to its input terminal is higher or not than the voltage level of the power supply Vcc.
As a prior art of the high voltage detector circuit, there is a circuit configuration disclosed in a Japanese patent application laid open as a Provisional Publication No. 190775/'83.
FIG. 3 is a circuit diagram illustrating the high voltage detector circuit of the prior art, comprising a serial connection of a pMOS transistor P1 and an nMOS transistor N1 connected between a ground and an input terminal 1 where a variable voltage supply Vpp is impressed, both gates of the pMOS transistor P1 and the nMOS transistor N1 coupled to a power supply Vcc and an output OUT is obtained from connection point of the pMOS transistor P1 and the nMOS transistor N1.
When the variable voltage supply Vpp not higher than the power supply Vcc is impressed to the input terminal 1, the pMOS transistor P1 becomes OFF and the nMOS transistor N1 becomes ON, the output OUT becoming at LOW level.
When the variable voltage supply Vpp supplies the high voltage, that is, Vpp&gt;Vcc+.vertline.Vthp.vertline., Vthp being threshold voltage of the pMOS transistor P1, both the pMOS transistor P1 and the nMOS transistor N1 become ON. So, by provided on-resistance of the pMOS transistor P1 and the nMOS transistor N1 appropriately, the output OUT is turned to HIGH level.
Thus, the variable voltage supply Vpp is discriminated whether it is higher or not than the power supply Vcc.
However, voltage level of the output OUT at HIGH level is determined by on-resistance ratio of the nMOS transistor N1 to the pMOS transistor P1 in the prior art of FIG. 3, and on-resistance of the nMOS transistor N1, the on-resistance ratio in consequence, is directly affected by voltage fluctuation of the power supply Vcc supplied to its gate. Therefore, there may be cases where the voltage level of the output OUT at HIGH level does not attain to a sufficient level because of low on-resistance of the nMOS transistor N1 when the power supply Vcc is comparatively high, resulting in malfunction of the LSI.
On the contrary, when the on-resistance of the nMOS transistor N1 is sufficiently high for preventing the above problem by making small the channel width/length ratio of the nMOS transistor N1, there arises another problem that the output OUT may become at HIGH level because of noise mingled in the variable voltage supply Vpp or leak current from the pMOS transistor P1 even when the variable voltage supply Vpp is supplying the low voltage, in case the power supply Vcc is comparatively low, resulting in malfunction too of the LSI.
There is also a problem of break of gate oxide of the pMOS transistor P1 caused by the high voltage impressed to the input terminal 1.